1. Field of the Invention
The present invention provides a method for making a self-aligned bit-line on a substrate.
2. Description of the Prior Art
A dynamic random access memory (DRAM) comprises an enormous amount of memory cells, each of which comprises a metal oxide semiconductor (MOS) and a capacitor. Each MOS and capacitor link with bit-lines through word lines to determine the location of each memory cell.
The design of a capacitor of a memory cell is based on two electric pole layers. The upper layer is a field plate and the lower layer is a storage node. These layers are separated by a cell dielectric layer. When one electric pole layer is subjected to a voltage, an electric charge of the corresponding value is induced in the other electric pole layer. The data storing and retrieving functions are achieved in this way. The lower layer storage node, in the form of a node contact acting as a connecting line, connects electrically with the drain of a MOS to store and retrieve data.
In order to raise the density of DRAM, when making lower layer storage nodes of the DRAM, landing pads are generally used in forming node contacts, which connect the MOS and capacitor with bit-lines. However, with advances in wafer production, the size of dynamic memory cells is being designed smaller and smaller. For this reason, the improvement and control of DRAM production processes has become an important subject in the field.
Please refer to FIG. 1 to FIG. 4. FIGS. 1 to 4 show the fabrication processes of a lower layer storage node 28 of a capacitor according to the prior art. As shown in FIG. 1, a semiconductor wafer 10 comprises a substrate 12, a landing pad 16 located on the substrate 12, a first dielectric layer 14 deposited on the surfaces of the substrate 12 and the landing pad 16, two bit-lines 18 located on the first dielectric layer 14 for data transmission, and a second dielectric layer 23 deposited over the surfaces of the two bit-lines 18 and the first dielectric layer 14. The two bit-lines are covered by a metallic silicide layer 20, which lowers the contact resistance of the surfaces of the bit-lines 18.
As shown in FIG. 2, according to the prior art method for making a node contact hole 26, the manufacturer forms a photoresist layer 24 on the surface of the second dielectric layer 23, and uses a lithographic process to pattern the location of the node contact hole 26 by forming a hole 25 in the photoresist layer 24. Next, the manufacturer performs an etching process, using the photoresist layer 24 as a hard mask, vertically removing the second dielectric layer 23 and then the first dielectric layer 16 along the hole 25, forming a node contact hole 26 on the landing pad 16 between the two bit-lines 18.
As shown in FIG. 3, after removing the photoresist layer 24, the manufacturer deposits a doped polysilicon layer over the surface of the substrate 10, which fills the node contact hole 26, and, with an etching back process or a chemical mechanical polishing (CMP) process, levels the doped polysilicon layer in the node contact hole 26 with the second dielectric layer 23, forming a node contact 27.
And as shown in FIG. 4, the manufacturer then evenly deposits an amorphous silicon layer over the surface of the substrate 10, and with a photolithographic process and an etching process forms a lower layer storage node 28 on the top of the node contact hole 26. A hemi-spherical grain (HSG) process is performed to increase the surface area of the lower layer storage node 28.
FIG. 5 shows a misalignment that can occur when making the lower layer storage node 28 of a capacitor according to the prior art. When etching the amorphous silicon layer to make the storage node 28, if the pattern of the location is not accurately transferred during the photolithographic process, a misalignment occurs. This misalignment allows the doped polysilicon in the node contact hole 26 (the node contact 27) to be etched off during the etching of the amorphous silicon. This results in a recess 29, which causes an insufficient thickness of the ONO layer over the doped polysilicon 27 in the recess 29 during later processes when forming a cell dielectric layer of oxide-nitride-oxide (ONO) over the storage node 28. This, in turn, results in a low-quality product. Additionally, since the node contact 27 is made after the two bit-lines 18, the line width of the bit-lines 18 must be made very narrow to avoid misalignment during the formation of the node contact hole 26. Unfortunately, the narrowing of line width results in a high resistance in the bit-lines 18, which affects the transmission speed, and which may even interrupt data transmission in the bit-lines 18.
Moreover, as shown in FIGS. 1 to 4, the process for making the lower layer storage nodes 28 of the DRAM requires two photolithographic processes to define the location of the node contact hole 26 and the storage node 28. For this reason, a landing pad has to be made before hand, which increases the DRAM manufacturing cost. Furthermore, with the size of the substrate decreasing, the precision of the photolithographic pattern transfer is lowered, and the subsequent yield rate is thus lowered.